Semiconductors are the backbone of the modern world. From smartphones to datacenters, medical devices to autonomous vehicles, semiconductors form the foundation of nearly every innovation in the digital age. Particularly, the rise of Generative AI has fueled an insatiable demand for computation and memory. Training Large Language Models (LLMs) depends on large clusters of GPU and High-Bandwidth Memory (HBM) stacks of multiple layers of DRAM, which are produced on leading-edge semiconductor nodes.
The industry is addressing the demand for continued scaling by embracing ≤3nm design nodes, novel 3D-transistor designs and stacked chip architectures, where transistors are vertically layered to increase processing power while reducing footprint and energy consumption. In the back-end, heterogeneous integration, and advanced, wafer-scale packaging technologies are employed to optimize performance, latency, power efficiency.
With shrinking feature sizes, more & thinner layers as well as increasing chip and package areas, the cost of damage of a wafer in the fab keeps rising continuously. At the same time, every sub-nanometer deviation during the manufacturing process (e.g., in line width, film thickness, overlay) can cause device failure or yield loss. As a result, Metrology and Inspection tools become even more vital. From patterning to packaging, every step must be measured, verified, and optimized. By characterizing materials and calibrating process equipment in real-time, Metrology and Inspection techniques are able to identify opportunities for yield improvement, ultimately lowering production costs. This comprehensive approach enhances the yield and cost-scaling of next-generation semiconductor devices, essentially keeping Moore's Law alive.
Laser-based metrology and inspection have become indispensable tools for achieving these goals — enabling manufacturers to visualize, quantify, and understand structures that are far smaller than the wavelength of visible light. Together with our customers, TOPTICA enables Semicon manufacturers to increase yield and throughput by optimizing key parameters like overlay accuracy, defect detection rates, wafer coverage and higher resolution across a variety of modalities including optical, e-Beam and THz.
